Integrated circuitry

ABSTRACT

Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

TECHNICAL FIELD

[0001] This invention relates generally to semiconductor processingmethods of forming resistors and diodes from semiconductive material,and to static random access memory (SRAM) cells incorporating resistors,and to other integrated circuitry incorporating resistors and diodes.

BACKGROUND OF THE INVENTION

[0002] One of the common elements required in electrical circuit devicesis the pull-up or pull-down resistor from an active device to one of thepower supply buses, typically referred to as Vcc. The pull-up is simpleif used to construct a circuit using discrete components in that allthat is required is selecting a resistor of the desired resistance andtolerance, connecting it between an active device such as an opencollector transistor and Vcc, and the transistor's output would bepulled up to Vcc once the transistor is forward biased. With the adventof integrated circuitry, however, fabricating a resistance onto a wafersubstrate, such as silicon or gallium arsenide, takes specialconsideration, particularly when resistivity and tolerances play animportant part in circuit operation.

[0003] For example, as SRAMs have evolved from the 4Kb memory arrays tomore densely packed array sizes, tolerances of pull-up resistances hadto be tightly controlled. In order to minimize standby current, manyfabrication processes adopted use an active device as the pull-up. InCMOS fabrication, it is common to see a PMOS transistor acting as thecurrent path between a memory cell access transistor and the powersupply bus. In this manner, the PMOS transistor can be gated “on” onlywhen the desired line is to be pulled up to Vcc and turned “off”otherwise. This in essence eliminates leakage current and minimizesstandby current for the SRAM device as a whole.

[0004] The main drawback to using an active device for a pull-up deviceis the amount of space required to fabricate the device. Now that theSRAM generation has grown to the 1Mb array size, die space is a criticalfactor to consider. Technology has basically pushed all types ofintegrated circuits to be more densely packed, and pull-ups are a commonelement in many circuit designs.

[0005] Although the invention primarily arose out of concerns associatedwith resistor fabrication in SRAM circuitry, the artisan will appreciateapplicability of the inventive technology elsewhere, with the inventiononly being limited by the accompanying claims appropriately interpretedin accordance with the doctrine of equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0007]FIG. 1 is a diagrammatic cross-sectional view of a semiconductorwafer fragment at one processing step in accordance with the invention.

[0008]FIG. 2 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 1.

[0009]FIG. 3 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 2.

[0010]FIG. 4 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 3.

[0011]FIG. 5 is a schematic representation of SRAM circuitry inaccordance with an aspect of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0013] The invention includes several aspects of forming resistor anddiode constructions. The invention also includes several aspects of SRAMand other integrated circuitry incorporating diodes and resistorsproduced according to the inventive methods, and produced according toother methods.

[0014] A semiconductor processing method of forming a resistorconstruction from semiconductive material is first described withreference to FIG. 1. Such illustrates a bulk semiconductor substrate 12,such as monocrystalline silicon, having a conductive diffusion region 14formed therein. Region 14 constitutes a node to which electricalconnection to a resistor is to be made. An electrically insulative layer16, typically borophosphosilicate glass (BPSG), is provided outwardlyrelative to node 14. A first opening 18, preferable in the configurationof a substantially vertical passageway, is provided therethrough overnode 14. First opening 18 has an opening width “A”. Node 14 can beprovided before provision layer 16 and opening 18, or after provision oflayer 16 and opening 18.

[0015] Referring to FIG. 2, a first layer 20 of semiconductive materialis chemical vapor deposited over electrically insulative layer 16 andwithin first opening 18 over node 14 to a thickness which is less thanone-half first opening width “A” to less than completely fill firstopening 18 with semiconductive material. Such thereby defines aremaining opening 22. An example semiconductive material of first layer20 is silicon, such as amorphously deposited silicon or polycrystallinesilicon. During or after deposition, first layer 20 can be provided witha first conductivity enhancing dopant impurity of a first “p” or “n”type. Layer 20 can also remain undoped at this point in the process.Accordingly, semiconductive material layer 20 has a first conductivityenhancing dopant concentration falling within a range of from 0 to somefirst value, with the first value typically being less than 1×10¹⁸ions/cm³. Greater values, such as 1×10²⁰ ions/cm³, would effectivelyinherently make layer 20 undesirably sufficiently electricallyconductive to provide negligible resistance effect.

[0016] Referring to FIG. 3, a second layer 24 of semiconductive materialis provided by chemical vapor deposition, or other technique, to withinremaining opening 22 and inside of first layer 20 to completely fillremaining opening 22 with semiconductive material. Thus, opening 18 islikewise completely filled with semiconductive material. Second layer 24is provided in one example with a second conductivity dopantconcentration which is greater than the first concentration. Thus, aconductivity enhancing impurity concentration gradient is providedwithin opening 18 which varies from a low concentration at an innerelevation 26 within opening 18 to a higher concentration at an outerelevation 28 within opening 18.

[0017] The conductivity enhancing dopants provided in first and secondlayers 20 and 24 can comprise the same or different conductivity “n” or“p” types. Further even if of the same type, the dopants might bedifferent, for example one being arsenic and one being phosphorus whichare both “n” type. When of the same type, the semiconductive materialeffectively filling opening 18 defines a substantially verticallyelongated resistor within opening/passageway 18, which is an ohmicelectrical contact with node 14. Where the conductivity enhancingdopants provided in first and second layers 20 and 24, respectively, areof different type, the result will be formation of a substantiallyvertically elongated diode provided within passageway 18 and in ohmicelectrical contact with node 14. The diode will effectively comprise tworegions 20 and 24 of semiconductive material which in combinationcompletely fill passageway 18.

[0018] In such instance, it may be desirable to provide each ofregions/layers 20 and 24 with about the same concentration level ofdopant impurity, and at greater than 1×10²⁰ ions/cm³, to form a highlyconductive diode. Alternately, it might be desirable to provide the tworegions/layers with different type and different concentration leveldopant impurities to effectively define a leaking or leaky diode, whichthen effectively functions as a resistor. Accordingly, in one aspect ofthe invention, a leaky diode construction also constitutes a verticallyelongated resistor within opening 18.

[0019] Ultimately, an outer layer of electrically conductive material isprovided outwardly of insulating layer 16 and patterned into aconductive line, with the elongated resistor or diode extending betweennode 14 and the formed conductive line. Such might be accomplished by anumber of methods. For example, the construction of FIG. 3 could beetched back by chemical mechanical polishing, or other means, back tothe upper surface of insulating layer 16. Subsequently, a metal or otherhighly conductive material can be deposited and patterned to form aline. More preferably, second layer 24 of semiconductive material isprovided to have a dopant concentration which is at least 1×10²⁰ions/cm³ and is deposited to a sufficient thickness to enable it to bepatterned into a conductive line 30 (FIG. 4). Accordingly in suchinstance, conductive line 30 comprises both first and second layers 20and 24, with outer layer 24 forming a highly conductive part thereof. Asilicide layer, such as WSi_(x) (not shown), might also be providedoutwardly of layer 24. In either event, the formed diode or resistorextends between node 14 and patterned conductive line 30. Processing inaccordance with the above described preferred method provides theadvantage of provision of a line and diode or resistor without addedmasking steps for the resistor or diode.

[0020] Alternate techniques are contemplated for provision ofsubstantially elongated vertically oriented resistors or diodes whichfill opening/passageway 18. For example in provision of a resistor,opening/passageway 18 might be filled in a substantially continuouschemical vapor deposition step. During such deposition, the conductivityenhancing impurity would be provided to the reactor at a rate varyingfrom, for example, a first lower rate to a second higher rate such thatthe outermost portion of the deposited layer has the desired highconductivity attributes, whereas lower regions have the desiredresistive attributes. The final resultant rate could be provided toproduce a dopant concentration at the outer regions of the depositedlayer which is at least 1×10²⁰ ions/cm³ to facilitate production of adesired highly conductive line outwardly of insulating layer 16.

[0021] A similar process could be utilized for formation of a diode. Forexample, a substantially continuous chemical vapor depositing step couldbe utilized to fill passageway/opening 18 and provide a layer thicknessoutwardly of insulating layer 16 sufficient for formation of aconductive line, and define an elongated diode within the passageway.For example, the chemical vapor depositing step could include firstfeeding a conductivity enhancing impurity of a first type into thereactor during deposition to provide semiconductive material of thefirst conductivity type at an inner elevation within the opening. Duringdeposition, the dopant feed to the reactor would be changed from thefirst feeding to a second feeding of a conductivity enhancing impurityof a second type to provide semiconductive material of the secondconductivity type at an outer elevation within the opening. Subsequentprovision of a conductive metal line by mere patterning, or by provisionof other conductive layers and patterning, could be provided.

[0022] Alternately in formation of a resistor, semiconductive materialmight be deposited atop insulating layer 16 and within opening 18 to beinherently undoped or very lightly doped as deposited. Subsequently, aconductivity enhancing dopant impurity might be driven into thesemiconductive material layer at least outwardly of the electricallyinsulative layer to a peak concentration of greater than or equal to1×10²⁰ ions/cm³. Subsequently, this semiconductive material layer wouldbe exposed to annealing conditions effective to diffuse dopant impuritywithin the semiconductive material from outwardly of the electricallyinsulative layer into the semiconductive material within the opening toeffectively form an elongated resistor in ohmic contact with node 14.The semiconductive material layer outwardly of the electricallyinsulative layer would thereafter be patterned into a conductive line,with the elongated resistor extending between node 14 and the conductiveline. Example annealing conditions include 950° C. for 20 seconds in anN₂ atmosphere. Alternately, the wafer might be exposed to sufficientthermal conditions throughout processing to inherently provide suchdesired dopant driving to deep within passageway 18.

[0023] For diode formation, an alternate process is also contemplated.Specifically, a single semiconductive material layer can be chemicallydeposited to within opening 18 and over layer 16 to completely fill suchopening. As deposited, the semiconductive material layer would beprovided with conductivity enhancing dopant impurity of a first typehaving an average concentration of about 1×10¹⁸ ions/cm³. After thechemical vapor depositing step, a conductivity enhancing dopant impurityof a second type can be provided into the outermost portions of thedeposited layer by ion implantation to a peak and overwhelmingconcentration of at least 1×10²⁰ ions/cm³. The substrate is then exposedto annealing conditions effective to diffuse second type dopant impuritywithin the semiconductive material from outwardly of the electricallyinsulative layer into the first type semiconductive material withinopening 18 to effectively form an elongated diode within the opening.

[0024] Integrated circuitry incorporating the above constructionswhereby a substantially vertically elongated resistor or diode extendsbetween a node and an outer conductive line is also contemplated.

[0025]FIG. 5 schematically illustrates one example of integratedcircuitry of an SRAM cell in accordance with the invention utilizing atleast one of the subject resistors. Such comprises a pair of first andsecond pull-down transistors 50 and 52, respectively. These includerespective drains 53, 54; respective sources 55, 56; and respectivegates 57, 58. Gate 57 of first pull-down transistor 50 is electricallycoupled to drain 54 of second pull-down transistor 52. Likewise, gate 58of second pull-down transistor 52 is electrically coupled to drain 53 offirst pull-down transistor 50. A ground node 58 and a Vcc node 60 areprovided. A first resistor 62 and a second resistor 64 electrically arecoupled with Ad Vcc node 60 via a patterned line. Drain 53 of firstpull-down transistor 50 electrically couples with Vcc node 60 throughfirst resistor 62. Drain 54 of second pull-down transistor 52electrically couples through second resistor 64 to Vcc node 60. A pairof cell access transistors 66 and 68 are also provided.

[0026] In the context of the previously described construction, thedescribed and illustrated resistor/leaking diode would constitute one orboth of resistors 62 and 64. Node 14 would constitute one of drains 53or 54. Node 14 could alternately be the outer surface of gate 57 or gate58. Patterned line 30 would be configured to extend to the suitablepower Vcc node.

[0027] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method of forming a resistor constructionfrom semiconductive material comprising the following steps: providing anode to which electrical connection to a resistor is to be made;providing an electrically insulative layer outwardly of the node;providing a first opening in the electrically insulative layer over thenode, the first opening having an opening width; providing a first layerof semiconductive material over the electrically insulative layer andwithin the first opening over the node to a thickness which is less thanone half the first opening width to less than completely fill the firstopening with semiconductive material and thereby define a remainingopening, the first layer within the first opening being provided with afirst conductivity enhancing dopant concentration falling within a rangefrom 0 to a first value; providing a second layer of semiconductivematerial to within the remaining opening and inside of the first layerto completely fill the remaining opening with semiconductive materialand define an elongated resistor within the first opening, the secondlayer within the remaining opening being provided with a secondconductivity dopant concentration which is greater than the firstconcentration; and providing an outer layer of electrically conductivematerial outwardly of the insulative layer and patterning the outerlayer into a conductive line, the elongated resistor extending betweenthe node and the conductive line.
 2. The semiconductor processing methodof forming a resistor construction of claim 1 wherein the node isprovided before providing the electrically insulative material andopening therethrough.
 3. The semiconductor processing method of forminga resistor construction of claim 1 wherein the conductivity enhancingdopants provided in the first and second layers are of the same type. 4.The semiconductor processing method of forming a resistor constructionof claim 1 wherein the conductivity enhancing dopants provided in thefirst and second layers are different but of the same type.
 5. Thesemiconductor processing method of forming a resistor construction ofclaim 1 wherein the conductivity enhancing dopants provided in the firstand second layers are of different types.
 6. The semiconductorprocessing method of forming a resistor construction of claim 1 whereinthe conductive line comprises the first and second layers.
 7. Thesemiconductor processing method of forming a resistor construction ofclaim 1 wherein the outer layer comprises semiconductive material havinga dopant concentration greater than or equal to the secondconcentration.
 8. The semiconductor processing method of forming aresistor construction of claim 1 wherein the second dopant concentrationis at least 1×10²⁰ ions/cm³, the outer layer consisting essentially ofthe first and second layers.
 9. A resistor produced according to theprocess of claim
 1. 10. A semiconductor processing method of forming aresistor construction from semiconductive material comprising thefollowing steps: providing a node to which electrical connection to aresistor is to be made; providing an electrically insulative layeroutwardly of the node; providing an opening in the electricallyinsulative layer over the node; within a chemical vapor depositionreactor, chemical vapor depositing a semiconductive material over theelectrically insulative layer and to within the opening in electricalcontact with the node to completely fill the opening and define anelongated resistor therewithin, the chemical vapor depositing stepincluding providing a conductivity enhancing impurity into the materialduring deposition, the conductivity enhancing impurity being provided tothe reactor at a rate varying from a first lower rate to a second higherrate to provide a conductivity enhancing impurity concentration gradientwithin the opening which varies from a low concentration at an innerelevation within the opening to a high concentration at an outerelevation within the opening; and providing an outer layer ofelectrically conductive material outwardly of the insulative layer andpatterning the outer layer into a conductive line, the elongatedresistor extending between the node and the conductive line.
 11. Thesemiconductor processing method of forming a resistor construction ofclaim 10 wherein the conductive line comprises the chemical vapordeposited semiconductive material.
 12. The semiconductor processingmethod of forming a resistor construction of claim 10 wherein the secondrate provides a dopant concentration at the outer elevation which is atleast 1×10²⁰ ions/cm³, the outer layer consisting essentially of thedeposited semiconductive material.
 13. A resistor produced according tothe process of claim
 10. 14. A semiconductor processing method offorming a resistor construction from semiconductive material comprisingthe following steps: providing a node to which electrical connection toa resistor is to be made; providing an electrically insulative layeroutwardly of the node; providing an opening in the electricallyinsulative layer over the node; within a chemical vapor depositionreactor, chemical vapor depositing a semiconductive material layer overthe electrically insulative layer and to within the opening inelectrical contact with the node to completely fill the opening; afterthe chemical vapor depositing step, providing a conductivity enhancingdopant impurity into the semiconductive material layer outwardly of theelectrically insulative layer to a peak concentration of at least 1×10²⁰ions/cm³; exposing the doped semiconductive material layer to annealingconditions effective to diffuse dopant impurity from outwardly of theelectrically insulative layer into the semiconductive material withinthe opening to effectively form an elongated resistor within theopening; and patterning the semiconductive material layer outwardly ofthe electrically insulative layer into a conductive line, the elongatedresistor extending between the node and the conductive line.
 15. Aresistor produced according to the process of claim
 14. 16. Asemiconductor processing method of forming a diode construction fromsemiconductive material comprising the following steps: providing a nodeto which electrical connection to a diode is to be made; providing anelectrically insulative layer outwardly of the node; providing a firstopening in the electrically insulative layer over the node, the firstopening having an opening width; providing a first layer ofsemiconductive material of a first type over the electrically insulativelayer and within the first opening over the node to a thickness which isless than one half the first opening width to less than completely fillthe first opening with semiconductive material of the first type andthereby define a remaining opening; providing a second layer ofsemiconductive material of a second type to within the remaining openingand inside of the first layer to completely fill the remaining openingwith semiconductive material of the second type and define an elongateddiode within the first opening; and providing an outer layer ofelectrically conductive material outwardly of the insulative layer andpatterning the outer layer into a conductive line, the elongated diodeextending between the node and the conductive line.
 17. Thesemiconductor processing method of forming a diode construction of claim16 wherein the conductive line comprises the first and second layers.18. The semiconductor processing method of forming a diode constructionof claim 16 wherein the outer layer comprises semiconductive materialhaving a dopant concentration greater than or equal to 1×10²⁰ ions/cm³.19. The semiconductor processing method of forming a diode constructionof claim 16 wherein the outer layer comprises semiconductive materialhaving a dopant concentration greater than or equal to 1×10²⁰ ions/cm³,the outer layer consisting essentially of the first and second layers.20. The semiconductor processing method of forming a diode constructionof claim 16 wherein the first and second layers have about the samedopant impurity concentration.
 21. The semiconductor processing methodof forming a diode construction of claim 16 wherein the first and secondlayers have different dopant impurity concentrations.
 22. A diodeproduced according to the process of claim
 16. 23. A semiconductorprocessing method of forming a diode construction from semiconductivematerial comprising the following steps: providing a node to whichelectrical connection to a diode is to be made; providing anelectrically insulative layer outwardly of the node; providing anopening in the electrically insulative layer over the node; within achemical vapor deposition reactor, chemical vapor depositing asemiconductive material over the electrically insulative layer and towithin the opening in electrical contact with the node to completelyfill the opening and define an elongated diode therewithin, the chemicalvapor depositing step including first feeding a conductivity enhancingimpurity of a first type into the reactor during deposition to providesemiconductive material of the first conductivity type at an innerelevation within the opening, the chemical vapor depositing stepincluding changing from the first feeding to a second feeding of aconductivity enhancing impurity of a second type into the reactor duringdeposition to provide semiconductive material of the second conductivitytype at an outer elevation within the opening; and providing an outerlayer of electrically conductive material outwardly of the insulativelayer and patterning the outer layer into a conductive line, theelongated diode extending between the node and the conductive line. 24.The semiconductor processing method of forming a diode construction ofclaim 23 wherein the conductive line comprises the chemical vapordeposited semiconductive material.
 25. The semiconductor processingmethod of forming a diode construction of claim 23 wherein the secondtype doped semiconductive material has a dopant concentration which isat least 1×10²⁰ ions/cm³, the outer layer comprising the depositedsecond type doped semiconductive material.
 26. A diode producedaccording to the process of claim
 23. 27. A semiconductor processingmethod of forming a diode construction from semiconductive materialcomprising the following steps: providing a node to which electricalconnection to a diode is to be made; providing an electricallyinsulative layer outwardly of the node; providing an opening in theelectrically insulative layer over the node; within a chemical vapordeposition reactor, chemical vapor depositing a semiconductive materiallayer over the electrically insulative layer and to within the openingin electrical contact with the node to completely fill the opening, thesemiconductive material layer being provided with conductivity enhancingimpurity doping of a first type having an average concentration of atleast 1×10¹⁷ ions/cm³; after the chemical vapor depositing step,providing a conductivity enhancing dopant impurity of a second type intothe semiconductive material layer outwardly of the electricallyinsulative layer to a peak concentration of at least 1×10²⁰ ions/cm³;exposing the doped semiconductive material layer to annealing conditionseffective to diffuse second type dopant impurity from outwardly of theelectrically insulative layer into the first type semiconductivematerial within the opening to effectively form an elongated diodewithin the opening; and patterning the semiconductive material layeroutwardly of the electrically insulative layer into a conductive line,the elongated diode extending between the node and the conductive line.28. A diode produced according to the process of claim
 27. 29.Integrated circuitry comprising: an electrically conductive node; anelectrically insulative layer lying outwardly of the node, theinsulative layer having a substantially vertical passageway formedtherethrough to the node; a substantially vertically elongated resistorwithin the passageway and in ohmic electrical contact with the node, theresistor comprising a semiconductive material having an averageconductivity enhancing dopant impurity concentration of less than orequal to about 5×10¹⁸ ions/cm³, the semiconductive material completelyfilling the passageway; and an outer conductive line of electricallyconductive material overlying the vertical resistor, the line being inohmic electrical contact with the vertical resistor, the verticalresistor extending between the conductive node and the conductive line.30. Integrated circuitry according to claim 29 wherein thesemiconductive material of the resistor comprises two regions havingdifferent conductivity type dopant impurity, the two regions havingdifferent average impurity concentrations.
 31. Integrated circuitryaccording to claim 29 wherein the outer conductive line comprises thesemiconductive material, but having an average dopant impurityconcentration of greater than or equal to about 1×10²⁰ ions/cm³. 32.Integrated circuitry according to claim 29 wherein the semiconductivematerial of the resistor has a conductivity enhancing impurityconcentration gradient within the passageway which varies from a lowconcentration at an inner elevation within the passageway to a highconcentration at an outer elevation within the passageway. 33.Integrated circuitry comprising: an electrically conductive node; anelectrically insulative layer lying outwardly of the node, theinsulative layer having a substantially vertical passageway formedtherethrough to the node; a substantially vertically elongated diodewithin the passageway and being in ohmic electrical contact with thenode, the diode comprising two regions of semiconductive material whichin combination completely fill the passageway, one of the regions beingconductively doped with a conductivity enhancing impurity of a firsttype, the other of the regions being conductively doped with aconductivity enhancing impurity of a second type; and an outerconductive line of electrically conductive material overlying thevertical diode, the line being in ohmic electrical contact with thevertical diode, the vertical diode extending between the conductive nodeand the conductive line.
 34. Integrated circuitry according to claim 33wherein the outer line comprises one of the regions of conductivelydoped semiconductive material.
 35. Integrated circuitry according toclaim 33 wherein the two regions have about the same dopant impurityconcentrations.
 36. Integrated circuitry according to claim 33 whereinthe two regions have different dopant impurity concentrations.
 37. AnSRAM cell comprising: a first pull down transistor having a gate, asource and a drain; a second pull down transistor having a gate, asource and a drain; the gate of the first pull down transistor beingelectrically coupled to the drain of the second pull down transistor;the gate of the second pull down transistor being electrically coupledto the drain of the first pull down transistor; a Vcc node; a firstresistor electrically coupled with the Vcc node; a second resistorelectrically coupled with the Vcc node; the drain of the first pull downtransistor being electrically coupled through the first resistor to theVcc node; the drain of the second pull down transistor beingelectrically coupled through the second resistor to the Vcc node; and atleast one of the first and second resistors comprising: an electricallyinsulative layer lying outwardly of the drain of the respective first orsecond pull down transistor, the insulative layer having a substantiallyvertical passageway formed therethrough to the respective first orsecond pull down transistor drain; a substantially vertically elongatedresistor filling the passageway and being in ohmic electrical contactwith the respective first or second pull down transistor drain, theresistor comprising a semiconductive material having an averageconductivity enhancing dopant impurity concentration of less than orequal to about 5×10¹⁸ ions/cm³, the semiconductive material completelyfilling the passageway; and an outer conductive Vcc line of electricallyconductive material overlying the vertical resistor and extending toVcc, the Vcc line being in ohmic electrical contact with the verticalresistor, the vertical resistor extending between the conductive lineand the respective first or second pull down transistor drain. 38.Integrated circuitry according to claim 37 wherein the semiconductivematerial of the resistor comprises two regions having differentconductivity type dopant impurity, the two regions having differentaverage impurity concentrations.
 39. Integrated circuitry according toclaim 37 wherein the outer conductive line comprises the semiconductivematerial, but having an average dopant impurity concentration of greaterthan or equal to about 1×10²⁰ ions/cm³.
 40. Integrated circuitryaccording to claim 37 wherein the semiconductive material of theresistor has a conductivity enhancing impurity concentration gradientwithin the passageway which varies from a low concentration at an innerelevation within the passageway to a high concentration at an outerelevation within the passageway.